1. Field
This patent document relates to a semiconductor design technology and, more particularly, to a semiconductor memory device which performs a repair operation.
2. Description of the Related Art
A repair operation for a defective cell in a semiconductor memory device may be categorized into those performed in the wafer state and those performed in the packaged state. The latter may be referred to as a post package repair (PPR) operation.
Semiconductor memory devices include fuse circuits capable of programming a repair address of a repair target memory cell that is defective. In the programming of the repair address of the repair target memory cell, the repair target memory cell's information is stored so that a redundancy memory cell may be used instead of the defective repair target memory cell.
Through the repair operation, when access to the repair target memory cell is attempted, the redundancy memory cell is accessed by reference to the programmed repair address.
FIG. 1 is a diagram illustrating fuse sets included in a conventional semiconductor memory device.
Referring to FIG. 1, a fuse circuit of the semiconductor memory device includes a plurality of normal fuse sets 111 to 115 and a PPR fuse set 116. The plurality of normal fuse sets 111 to 115 store the repair address information in the semiconductor memory device while in the wafer state, i.e. during the fabrication of the semiconductor memory device. The PPR fuse set 116 is allocated to store the repair address information in the semiconductor memory device while it is in the packaged state, i.e. after the fabrication of the semiconductor memory device.
The PPR operation is performed in response to an external command instructing the semiconductor memory device to perform a repair operation. The semiconductor memory device enters the PPR mode and performs a PPR operation of storing the repair address information, which is applied by an external source, in the PPR fuse set 116.
The PPR mode may include a soft-post package repair (Soft-PPR; SPPR) mode in which the semiconductor memory device latches the repair address information applied from outside (i.e. from an external device or host) in a register or latch unit. Through the SPPR mode, the time required for the repair operation may be reduced. During the SPPR mode, however, when power supplied to the semiconductor memory device is cutoff, the effects of the repair operation, for example, the repair address, disappears. That is, the repair operation during the SPPR mode temporarily stores the repair address information applied from outside.
FIG. 2 is a diagram illustrating a fuse circuit of a semiconductor memory device.
Referring to FIG. 2, a fuse circuit of the semiconductor memory device includes a normal fuse set 210, a PPR fuse set 220, a first comparison unit 230, and a second comparison unit 240.
FIG. 2 exemplarily shows that the normal fuse set 210 already stores addresses ADDRESS<4> and ADDRESS<6> as the repair address information through the repair operation during the fabrication of the semiconductor memory device.
The first comparison unit 230 compares an input address EX_ADD and the repair address information stored in the normal fuse set 210. The first comparison unit 230 enables a first match signal MATCH_NM when the repair address information, for example ADDRESS<4>, stored in the normal fuse set 210 is the same as the input address EX_ADD. The semiconductor memory device can normally access a redundancy memory cell in response to the first match signal MATCH_NM.
However, when a failure occurs in the redundancy memory cell corresponding to the repair address ADDRESS<4> of the repair target memory cell in the packaged state, a user of the semiconductor memory device may store the address ADDRESS<4> in the PPR fuse set 220 as the repair address through the SPPR mode even though the address ADDRESS<4> is already stored in the normal fuse set 210.
Then, when the semiconductor memory device receives the address ADDRESS<4> as an input address EX_ADD from outside, the first and second comparison units 230 and 240 simultaneously generate first and second match signals MATCH_NM and MATCH_PPR indicating that the address ADDRESS<4> stored in the normal fuse set 210 and the address ADDRESS<4> latched in the PPR fuse set 220 are the same as the input address EX_ADD. As a result, a redundancy memory cell corresponding to the first match signal MATCH_NM and a redundancy memory cell corresponding to the second match signal MATCH_PPR are accessed at the same time.
In short, when the repair address information stored in the PPR fuse set 220 during the SPPR mode coincides with the repair address information stored in the normal fuse set 210 during the fabrication of the semiconductor memory device, the redundancy memory cells corresponding to the same repair address information stored both in the PPR fuse set 220 and the normal fuse set 210 may be accessed at the same time. Then, a read failure may occur during a normal operation.